Designing of semiconductor integrated circuits involves logic synthesis to convert design information from register transfer level (RTL) to gate level (netlist). In the logic synthesis process, RTL design information, timing conditions, design rule check (DRC), etc. are used to decide which circuit to implement functions.
A timing condition that is given at the time of the logic synthesis indicates a design margin relevant to timing (hereinafter, referred to as timing margin). Variations in delay time of clock signals, due to clock skew, clock on chip variation (OCV), crosstalk delay, a gap between wiring delay estimate and real wiring delay, phase locked loop (PLL) jitter, and other reasons may not be considered at the time of logic synthesis. Hence, at the time of logic synthesis, a timing margin is set in the timing condition on the basis of the sum of the worst-case values of delay time variations generated in the above respective delay variation elements, such as clock skew.
See, for example, Japanese Laid-open Patent Publication Nos. 2003-76729, 11-145297, and 6-19999.
In the meantime, when a timing margin is set as described above, a timing constraint to be satisfied becomes severe, and a logic synthesis tool generates a netlist by selecting comparatively high-speed circuits, so as to satisfy the constraint. Such a circuit tends to have a large circuit area. Hence, a problem is to reduce a circuit area of a semiconductor integrated circuit.